1. Field of the Invention
The present invention relates to an electronic semiconductor device, and more specifically to a ball grid array (BGA) package.
2. Description of the Related Art
Many electronic devices include integrated circuits mounted on printed circuit boards. Integrated circuits, or dies, have been typically packaged for ease of installation on the printed circuit board. Small packages provide a competitive advantage in consumer products by limiting the size of the printed circuit board to enhance the portability of the electronic devices.
Integrated circuits typically have leads, or bond wires, for connection to a printed circuit board. However, as integrated circuits have become more complex, the number of leads has increased. This increase in lead count, coupled with the reduction in package size, has lead to leads having a finer pitch. The finer lead pitch allows a small package size and the resulting high density board assembly. However, the fine pitch of the leads has made it difficult to assemble the board.
Ball grid array (BGA) packages allow small integrated circuits to be connected easily on the "mother" circuit board. The die is mounted on one surface of a substrate, and a number of electrically conductive traces or wires are patterned onto a surface of the substrate. More particularly, fine pitch traces radiate outward from the die, with each trace connected, at one end, to the lead from the die and, at the other end, to a bond pad to which a solder ball is electrically connected.
A circuit board typically has an insulating layer covering a layer of conductive interconnects. Ball grid array packages are typically mounted onto a circuit board by reflowing the solder balls into holes in the insulating layer to connect with the conductive interconnect layer of the printed circuit board. Solder balls typically widen slightly during connection to the printed circuit board, during thermal cycling of the die during testing, and/or during operation of the device. Therefore, the solder balls are initially spaced apart a minimum distance from one another, from the traces to which connection is to be prevented, and from the die, even for smaller packages.
Also, a thicker substrate having a recess or cavity in the upper surface in a "cavity up" BGA has been used where the die is mounted within the cavity, allowing a stiffer package without increasing overall profile height. This package stiffness enhances the coplanarity of the solder balls. To achieve greater stiffness, package designers have added stiffeners, additional substrates, and thicker substrates. "Cavity up" BGA have experienced uncompensated inductances due to both the bending of the traces through the vias and the bending of the traces around the solder balls on the lower surface, particularly at higher frequencies. In particular, the "cavity up" substrate has typically included traces on the upper surface, connected to the die, which passed through small through-holes or "vias" in the substrate to the lower surface of the substrate. The traces on the lower surface of the substrate extend from the vias to connect with the solder balls. Like the "up" BGA, because the solder balls have been distributed on the lower surface of the substrate, the routing of the traces on the lower surface of the substrate was not rectilinear, and often when routing the traces they were "bent" around some other solder balls en route to the desired solder ball.
The uncompensated inductances due to the bending of the traces through the vias was reduced in "cavity down" BGA, since a cavity on the lower surface of a substrate allowed a die to be mounted on the cavity ceiling, almost completely within the substrate. The leads of the integrated circuit or die formed bond wire loops connecting directly to the traces on the lower surface of the substrate, thereby eliminating both the upper traces and the vias through the substrate.
For example, referring to FIG. 1, a "cavity down" ball grid array (BGA) package includes a substrate 102, having an upper surface 102a and a lower surface 102b, and a recessed central cavity 104 in the lower surface 102b. The substrate 102 is made of FR4, a thin printed wiring board (PWB) material. A semiconductor die 106 is mounted to the ceiling or top of the cavity 104 by a heat-dissipating, epoxy adhesive. The lower surface 102b of the substrate 102 is covered with a patterned lead frame of copper, forming a lead frame of traces 112 that extend outwardly from the edge of the cavity 104 with each trace ending on a bond pad 114a metallurgically wetted to a solder ball 114. The traces 112 have been typically very fine patterns of metallic conductors, each trace providing electrical connection between one of the solder balls 114 and a corresponding bond wire 116 at the edge of the cavity 104. The solder balls 114 are grouped near the periphery of the lower surface 102b of the substrate 102, for protection from possible widening.
The bond wire 116 at the edge of the cavity 104 is connected by either inner lead bonding (either thermosonic or thermocompression) or wire-bonding to a lead on the die 106. Although not shown in FIG. 1, the substrate 102 may have several layers of traces 112 separated by dielectric layers, each trace 112 of each lead frame being separately connected to a bond wire 116. The bond wires 116 loop height therefore create a "bump" 116a on the lower surface 102b of the substrate 102. Even when only one lead frame of traces 112 is included, the bond wires 116 create a bump on the lower surface 102b of the substrate 102. If desired, a heat sink 118 schematically shown in FIG. 1, can be positioned to pass through the substrate 102 into the cavity 104, to remove heat generated by the die 106. "Cavity down" BGA are also desired due to their improved thermal performance. The lower surface of the die 106 adheres directly to the thermally conductive heat spreader. This facilitates the use of an additional heat sink 108, externally attached, as well.
While "cavity down" ball grid array packages have reduced the uncompensated inductances caused by bending of the traces 112 through the vias, they have not eliminated the significant uncompensated impedance created by the bending of the traces 112 around the solder balls 114 on the lower surface 102b. This problem of bending in the routing of traces has been exacerbated as pin count (and consequently solder ball count) has increased. As can now be seen, the solder balls 114 nearer to the cavity obstruct a direct, rectilinear path between the bond wires 116 and the solder balls 114 nearer to the periphery of the substrate 102.
Yet another problem with ball grid array routing is the tight dimensional tolerance for implementing the traces 112. As the number of solder balls 114 has increased, the distance between adjacent solder balls 114 has diminished, leaving very little space for the traces 112. As package size was reduced and pin count increased, proportionally more of the package surface area was covered with solder balls, and hence the trace routing became more difficult to implement between the solder balls.
Another problem with existing ball grid arrays involve the encapsulation of the lower surface 102b of the substrate 102. Encapsulating the package in a resin, liquid, or other protective material dispensed within the cavity has provided some measure of physical, electrical and thermal protection of the package from other packages on the shared printed circuit board. Referring again to FIG. 1, once fabricated, the package is encapsulated giving rise to at least three problems. First, the encapsulant 110 can amass in the vicinity of the bond wires 116 on the lower surface of the substrate 102, that could create an uneven surface or bump 116a that reduces the coplanarity of the solder balls 114. Solder balls 114 closer to the bump 116a may be prevented from coming into contact with the circuit board by the presence of the bump, even though other solder balls 114 may make appropriate connection. Second, the mass of encapsulant 110 intrudes on the standoff of the package and may prevent the solder balls 114 from reaching the circuit board. The standoff of a package is the distance between the lower surface the package and the upper surface of the circuit board. Third, the spreading of encapsulant 110 is difficult to control, and encapsulant 110 may come into contact with the bond pads 114a, thereby contaminating the bond pads 114a.
It will be recognized by one skilled in the art that other ball grid array structures are known. Some have been "cavity up," some have been "cavity down," and some have multiple cavities on the same substrate. Additionally, some have more than one substrate. Many of these have particular advantages over the prior art described, but these variations of designs do not eliminate the basic problem in routing and the thickness of the encapsulant 110 and the consequent reduction in profile standoff during the solder reflow to bond the package to the external printed circuit board.